The present invention relates to power driver circuits for controlling the operation of a semiconductor switching device in response to control signal inputs from a control circuit. In one aspect, the present invention relates to a method and device for turning on a latching switch in the power driver circuit at a speed that is independent of the rate of change of the control signal input voltage. In another aspect, the present invention is responsive to the control signal to control the operation of the latching switch by the semiconductor switching device.
It is to be understood that the terms used to describe elements of various embodiments of the present invention are not intended to limit the invention to those particular named elements where a functional equivalent exists. For example, even though the term "MOSFET" is used in the following description to describe the semiconductor switching device, the present invention also relates to other semiconductor switching devices such as FETs, IGBTs MOS controlled thyristors, (MCT's), BJTs, triacs, SCRs, GTO thyristors, and SITs. The gate of the MOSFET has equivalent structures in these devices and reference to a gate herein includes the equivalent structure in these devices. Further, by way of example, the term "SCR" as used in the following description also refers to other latching switches as are known in the art.
Semiconductor switching devices typically are used to regulate power that is to be switched on and off at a frequency determined by a control circuit. A power driver circuit typically acts as a buffer between the control circuit and the switching device and translates control signals from the control circuit into signals that can turn the switching device on and off at the requisite frequency. For example, a switchmode power supply (a semiconductor switching device) may be operated by a pulse transformer (a control circuit) at 300 kHz through a power driver circuit.
As is known, semiconductor switching devices consume more power during the period of transition between its two on and off steady states than during either the on or off periods. Therefore, one way to improve the efficiency of a switching device operating at a particular frequency is to decrease the length of the periods in which the switching device is in transition.
The background of the present invention may be further understood with reference to FIG. 1, in which a power driver circuit of the prior art may be seen. A FET 10 may be driven by a control circuit 12 through a power driver circuit 14. To turn the FET 10 on, current is provided to the gate 16 of the FET thereby allowing the FET to conduct a current between its source 18 and drain 20. To turn the FET off and stop current flow between its source and drain, current is pulled from the gate 16.
The control signal is applied through D1 to charge C1 in one cycle and the FET is turned on when a control signal from control circuit 12 in a second cycle is routed through D2 and D3 to the base of BJT Q1, turning Q1 on. When Q1 is on, current from C1 is applied to the gate 16 to turn on the FET.
The FET is turned off when the current at gate 16 is drained through a latching switch 22 (the latching switch in FIG. 1 is formed by the combination of BJTs Q2 and Q3). The current from the FET gate 16 is drained when latching switch 22 is turned on, with latching switch 22 being turned on when the voltage across R2 is Q1 V.sub.BE below the gate voltage of the FET. In other words, R2 provides a trigger current for turning on the latching switch 22.
The rate at which the FET turns off, and thus the length of the period of transition, is controlled by the speed at which the charge on the gate 16 is drained. The speed at which the charge is drained from the gate 16 is, in turn, controlled by the speed at which latching switch 22 turns on.
Typically, a latching switch, such as an SCR, must build up a charge before turning on. The trigger of the prior art (R2) which controls conduction of the latching switch derives current from the control signal, and thus the speed at which the latching switch conducts is a function of the character in the control signal.
In contrast, the latching switch of the present invention is independent of the character of the control signal.
More specifically, the latching switch that controls the turn off rate of the FET is turned on immediately following a change in polarity of the control signal by drawing a small portion of the current from the FET as a trigger current to both the anode gate and the cathode gate of the latching switch.
In contrast to the known prior art which provides a triggering signal to only one side of the latching switch, triggering signals are provided to both sides of the latching switch to speed its conditioning for conduction.
This distinction may be more clearly seen with reference to FIGS. 2 and 3 where the present invention (FIG. 2) uses a trigger signal from the FET gate to turn on latching switch 2 in contrast to the prior art (FIG. 3), where the switch 2 is turned on by the control signal.
With reference to FIG. 3, power from the control circuit (possibly by way of capacitor C1 of FIG. 1) is applied through Switch 1 to the gate of the FET. Conduction (or turn on) of the FET is thus achieved by the application of a control signal from the control circuit to the control terminal of Switch 1, and the application of a control signal to the trigger switch which insures non-conduction of the Switch 2 which permits the accumulation of charge on the FET gate.
The turn off of the FET is achieved by reversal of the conduction states of Switch 1 and Switch 2 under the control of the control circuit, Switch 1 opening to remove power to the FET gate and Switch 2 closing to drain the charge from the FET gate. However, the trigger switch is not immediately responsive to the reversal of the polarity of the control signal and depends on its amplitude. Thus the initiation of FET turn off is a function of the character of the control signal and lags the polarity reversal.
As shown in FIG. 2, the turn on of the FET is achieved in the same manner as described above in connection with FIG. 3. However, turn off is accelerated because the trigger switch in FIG. 2 is immediately responsive to the polarity reversal of the control circuit without regard to its amplitude to apply a trigger signal from the gate of the FET to Switch 2, thereby immediately initiating conduction of Switch 2. Turn off of the FET is thus independent of the character of the control signal.
Accordingly, it is an object of the present invention to provide a novel method and device for improving the efficiency of semiconductor switching devices.
It is a further object of the present invention to provide a novel method and device for providing triggering a latching switch in a power driver circuit.
It is yet a further object of the present invention to provide a novel method and device in which current from the semiconductor switching device gate is used to initiate operation of a latching switch in a power driver circuit.
It is still a further object of the present invention to provide a novel method and device for decreasing the length of the periods of transition between the two steady states of a semiconductor switching device.
It is another object of the present invention to provide a novel power driver circuit in which a high speed diode and a high speed SCR contribute to decreasing the length of the period of transition between the two steady states of a semiconductor switching device.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings and the following detailed description of preferred embodiments.